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lt3757 1 3757fc n wide input voltage range: 2.9v to 40v n positive or negative output voltage programming with a single feedback pin n current mode control provides excellent transient response n programmable operating frequency (100khz to 1mhz) with one external resistor n synchronizable to an external clock n low shutdown current < 1a n internal 7.2v low dropout voltage regulator n programmable input undervoltage lockout with hysteresis n programmable soft-start n small 10-lead dfn (3mm 3mm) and thermally enhanced 10-pin msop packages typical a pplica t ion descrip t ion boost, flyback, sepic and inverting controller the lt ? 3757 is a wide input range, current mode, dc/dc controller which is capable of generating either positive or negative output voltages. it can be configured as either a boost, flyback, sepic or inverting converter. the lt3757 drives a low side external n-channel power mosfet from an internal regulated 7.2v supply. the fixed frequency, current-mode architecture results in stable operation over a wide range of supply and output voltages. the operating frequency of lt3757 can be set with an external resistor over a 100khz to 1mhz range, and can be synchronized to an external clock using the sync pin. a low minimum operating supply voltage of 2.9v, and a low shutdown quiescent current of less than 1a, make the lt3757 ideally suited for battery-operated systems. the lt3757 features soft-start and frequency foldback functions to limit inductor current during start-up and output short-circuit. high efficiency boost converter fea t ures a pplica t ions n automotive and industrial boost, flyback, sepic and inverting converters n telecom power supplies n portable electronic equipment efficiency sense lt3757 v in v in 8v to 16v 10f 25v x5r v out 24v 2a 0.01 41.2k 300khz gate fbx gnd intv cc shdn/uvlo sync rt ss vc 200k 43.2k 0.1f 22k 6.8nf 10h 3757 ta01a 226k 16.2k 4.7f 10v x5r 10f 25v x5r 47f 35v 2 + output current (a) 0.001 efficiency (%) 30 50 40 60 70 80 90 100 0.01 0.1 1 3757 ta01b 10 v in = 8v v in = 16v l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks and no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
lt3757 2 3757fc p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , shdn /uvlo (note 6) ......................................... 4 0v intv cc .................................................... v in + 0.3v, 20v gate ........................................................ in tv cc + 0.3v sync .......................................................................... 8v vc, ss ......................................................................... 3v rt ............................................................................ 1. 5v sense .................................................................... 0.3v fbx ................................................................. C 6v to 6v (note 1) top view dd package 10-lead (3mm 3mm) plastic dfn 10 9 6 7 8 4 5 11 3 2 1 v in shdn/uvlo intv cc gate sense vc fbx ss rt sync t jmax = 125c, ja = 43c/w exposed pad (pin 11) is gnd, must be soldered to pcb 1 2 3 4 5 vc fbx ss rt sync 10 9 8 7 6 v in shdn/uvlo intv cc gate sense top view mse package 10-lead plastic msop 11 t jmax = 150c, ja = 40c/w exposed pad (pin 11) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt3757edd#pbf lt3757edd#trpbf ldyw 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3757idd#pbf lt3757idd#trpbf ldyw 10-lead (3mm 3mm) plastic dfn C40c to 125c lt3757emse#pbf lt3757emse#trpbf ltdyx 10-lead (3mm 3mm) plastic msop C40c to 125c lt3757imse#pbf lt3757imse#trpbf ltdyx 10-lead (3mm 3mm) plastic msop C40c to 125c lt3757hmse#pbf lt3757hmse#trpbf ltdyx 10-lead (3mm 3mm) plastic msop C40c to 150c lt3757mpmse#pbf lt3757mpmse#trpbf ltdyx 10-lead (3mm 3mm) plastic msop C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating temperature range (notes 2, 8) lt3757e ............................................. C4 0c to 125c lt3757i .............................................. C4 0c to 125c lt3757h ............................................ C 40c to 150c lt3757mp ......................................... C 55c to 150c storage temperature range dfn .................................................... C 65c to 125c msop ................................................ C 65c to 150c lead temperature (soldering, 10 sec) msop ............................................................... 3 00c
lt3757 3 3757fc e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at t a = 25c. v in = 24v, shdn /uvlo = 24v, sense = 0v, unless otherwise noted. parameter conditions min typ max units v in operating range 2.9 40 v v in shutdown i q shdn/uvlo = 0v shdn/uvlo = 1.15v 0.1 1 6 a a v in operating i q v c = 0.3v, r t = 41.2k 1.6 2.2 ma v in operating i q with internal ldo disabled v c = 0.3v, r t = 41.2k, intv cc = 7.5v 280 400 a sense current limit threshold l 100 110 120 mv sense input bias current current out of pin C65 a error amplifier fbx regulation voltage (v fbx(reg) ) v fbx > 0v (note 3) v fbx < 0v (note 3) l l 1.569 C0.816 1.6 C0.80 1.631 C0.784 v v fbx overvoltage lockout v fbx > 0v (note 4) v fbx < 0v (note 4) 6 7 8 11 10 14 % % fbx pin input current v fbx = 1.6v (note 3) v fbx = C0.8v (note 3) C10 70 100 10 na na transconductance g m (?i vc /?v fbx ) (note 3) 230 s vc output impedance (note 3) 5 m v fbx line regulation [?v fbx /(?v in ? v fbx(reg) )] v fbx > 0v, 2.9v < v in < 40v (notes 3, 7) v fbx < 0v, 2.9v < v in < 40v (notes 3, 7) 0.002 0.0025 0.056 0.05 %/ v %/ v vc current mode gain (?v vc /?v sense ) 5.5 v/ v vc source current v fbx = 0v, v c = 1.5v C15 a vc sink current v fbx = 1.7v v fbx = C0.85v 12 11 a a oscillator switching frequency r t = 41.2k to gnd, v fbx = 1.6v r t = 140k to gnd, v fbx = 1.6v r t = 10.5k to gnd, v fbx = 1.6v 270 300 100 1000 330 khz khz khz rt voltage v fbx = 1.6v 1.2 v minimum off-time 220 ns minimum on-time 220 ns sync input low 0.4 v sync input high 1.5 v ss pull-up current ss = 0v, current out of pin C10 a low dropout regulator intv cc regulation voltage l 7 7.2 7.4 v intv cc undervoltage lockout threshold falling intv cc uvlo hysteresis 2.6 2.7 0.1 2.8 v v intv cc overvoltage lockout threshold 16 17.5 v intv cc current limit v in = 40v v in = 15v 30 40 95 55 ma ma intv cc load regulation (?v intvcc /v intvcc ) 0 < i intvcc < 20ma, v in = 8v C0.9 C0.5 % intv cc line regulation ?v intvcc /(v intvcc ? ?v in ) 8v < v in < 40v 0.008 0.03 %/v dropout voltage (v in C v intvcc ) v in = 6v, i intvcc = 20ma 400 mv
lt3757 4 3757fc temperature (c) ?75 ?50 1580 1585 regulated feedback voltage (mv) 1590 1605 1600 0 50 75 1595 ?25 25 100 150125 3757 g01 v in = 40v v in = 24v v in = 8v v in = intv cc = 2.9v shdn/uvlo = 1.33v temperature (c) regulated feedback voltage (mv) ?802 ?800 ?798 ?788 ?790 ?792 ?794 ?804 ?796 3757 g02 ?75 ?50 0 50 75 ?25 25 100 150125 v in = 40v v in = 24v v in = 8v v in = intv cc = 2.9v shdn/uvlo = 1.33v typical p er f or m ance c harac t eris t ics positive feedback voltage vs temperature, v in negative feedback voltage vs temperature, v in quiescent current vs temperature, v in t a = 25c, unless otherwise noted. e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temp- erature range, otherwise specifications are at t a = 25c. v in = 24v, shdn /uvlo = 24v, sense = 0v, unless otherwise noted. parameter conditions min typ max units intv cc current in shutdown shdn /uvlo = 0v, intv cc = 8v 16 a intv cc voltage to bypass internal ldo 7.5 v logic inputs shdn /uvlo threshold voltage falling v in = intv cc = 8v l 1.17 1.22 1.27 v shdn /uvlo input low voltage i(v in ) drops below 1a 0.4 v shdn/uvlo pin bias current low shdn/uvlo = 1.15v 1.7 2 2.5 a shdn/uvlo pin bias current high shdn/uvlo = 1.30v 10 100 na gate driver t r gate driver output rise time c l = 3300pf (note 5), intv cc = 7.5v 22 ns t f gate driver output fall time c l = 3300pf (note 5), intv cc = 7.5v 20 ns gate v ol 0.05 v gate v oh intv cc C0.05 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3757e is guaranteed to meet performance specifications from the 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3757i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3757h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. the lt3757mp is 100% tested and guaranteed over the full C55c to 150c operating junction temperature range. note 3: the lt3757 is tested in a feedback loop which servos v fbx to the reference voltages (1.6v and C0.8v) with the vc pin forced to 1.3v. note 4: fbx overvoltage lockout is measured at v fbx(overvoltage) relative to regulated v fbx(reg) . note 5: rise and fall times are measured at 10% and 90% levels. note 6: for v in below 6v, the shdn/uvlo pin must not exceed v in . note 7: shdn/uvlo = 1.33v when v in = 2.9v. note 8: the lt3757 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. ?75 ?50 0 50 75 ?25 25 100 150125 temperature (c) 1.4 quiescent current (ma) 1.6 1.8 1.5 1.7 3757 g03 v in = 40v v in = 24v v in = intv cc = 2.9v
lt3757 5 3757fc typical p er f or m ance c harac t eris t ics switching frequency vs temperature sense current limit threshold vs temperature sense current limit threshold vs duty cycle shdn/uvlo threshold vs temperature shdn /uvlo current vs voltage shdn/uvlo hysteresis current vs temperature dynamic quiescent current vs switching frequency r t vs switching frequency normalized switching frequency vs fbx t a = 25c, unless otherwise noted. fbx voltage (v) ?0.8 0 normalized frequency (%) 20 40 60 80 120 ?0.4 0 0.4 0.8 3757 g06 1.2 1.6 100 ?75 ?50 0 50 75 ?25 25 100 150125 temperature (c) 100 sense threshold (mv) 105 110 115 120 3757 g08 duty cycle (%) 0 95 sense threshold (mv) 105 20 40 8060 115 100 110 100 3757 g09 shdn /uvlo voltage (v) 0 0 shdn/uvlo current (a) 20 10 20 30 40 10 30 40 3757 g11 ?75 ?50 0 50 75 ?25 25 100 150125 temperature (c) 1.6 i shdn / uvlo (a) 1.8 2.0 2.2 2.4 3757 g12 switching frequency (khz) 0 0 i q (ma) 15 20 35 300 500 600 700 10 5 25 30 100 200 400 900800 1000 3757 g04 c l = 3300pf switching frequency (khz) 0 10 r t (k) 100 1000 300 500 600 700 100 200 400 900800 1000 3757 g05 ?75 ?50 0 50 75 ?25 25 100 150125 temperature (c) 270 switching frequency (khz) 280 290 300 310 330 3757 g07 320 r t = 41.2k ?75 ?50 0 50 75 ?25 25 100 150125 temperature (c) 1.18 shdn/uvlo voltage (v) 1.22 1.24 1.26 1.28 1.20 3757 g10 shdn/uvlo falling shdn/uvlo rising
lt3757 6 3757fc typical p er f or m ance c harac t eris t ics intv cc line regulation intv cc dropout voltage vs current, temperature gate drive rise and fall time vs intv cc typical start-up waveforms intv cc vs temperature intv cc minimum output current vs v in intv cc load regulation t a = 25c, unless otherwise noted. gate drive rise and fall time vs c l fbx frequency foldback waveforms during overcurrent ?75 ?50 0 50 75 ?25 25 100 150125 temperature (c) 7.0 intv cc (v) 7.1 7.2 7.3 7.4 3757 g13 v in (v) 0 intv cc voltage (v) 35 7.25 7.20 10 20 5 15 25 30 40 7.15 7.10 7.30 3757 g16 c l (nf) 0 time (ns) 60 70 80 50 40 5 1510 20 25 30 10 0 30 90 20 3757 g18 rise time intv cc = 7.2v fall time intv cc (v) 3 time (ns) 20 25 15 10 9 6 12 15 5 0 30 3757 g19 c l = 3300pf rise time fall time 2ms/div v out 5v/div i l1a + i l1b 5a/div 3757 g20 v in = 12v page 31 circuit 50s/div page 31 circuit v out 10v/div v sw 20v/div i l1a + i l1b 5a/div 3757 g21 v in = 12v intv cc load (ma) 0 6.8 7 7.1 7.2 7.3 20 40 50 60 6.9 10 30 70 3757 g15 intv cc voltage (v) v in = 8v intv cc load (ma) 0 dropout voltage (mv) 500 600 300 400 200 10 5 15 20 100 0 700 3757 g17 150c 125c 25c 0c ?55c 75c v in = 6v v in (v) 0 intv cc current (ma) 50 60 70 40 3757 g14 40 30 0 10 10 20 30 5 15 25 35 20 90 80 t j = 150c intv cc = 6v intv cc = 4.5v
lt3757 7 3757fc p in func t ions vc (pin 1): error amplifier compensation pin. used to stabilize the voltage loop with an external rc network. fbx (pin 2): positive and negative feedback pin. receives the feedback voltage from the external resistor divider across the output. also modulates the frequency during start-up and fault conditions when fbx is close to gnd. ss (pin 3): soft-start pin. this pin modulates compensation pin voltage (vc) clamp. the soft-start interval is set with an external capacitor. the pin has a 10a (typical) pull-up current source to an internal 2.5v rail. the soft-start pin is reset to gnd by an undervoltage condition at shdn/ uvlo, an intv cc undervoltage or overvoltage condition or an internal thermal lockout. rt (pin 4): switching frequency adjustment pin. set the frequency using a resistor to gnd. do not leave this pin open. sync (pin 5): frequency synchronization pin. used to synchronize the switching frequency to an outside clock. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than the sync pulse frequency. tie the sync pin to gnd if this feature is not used. sync is ignored when fbx is close to gnd. sense (pin 6): the current sense input for the control loop. kelvin connect this pin to the positive terminal of the switch current sense resistor in the source of the n- channel mosfet. the negative terminal of the current sense resistor should be connected to gnd plane close to the ic. gate (pin 7): n-channel mosfet gate driver output. switches between intv cc and gnd. driven to gnd when ic is shut down, during thermal lockout or when intv cc is above or below the ov or uv thresholds, respectively. intv cc (pin 8): regulated supply for internal loads and gate driver. supplied from v in and regulated to 7.2v (typi- cal). intv cc must be bypassed with a minimum of 4.7f capacitor placed close to pin. intv cc can be connected directly to v in , if v in is less than 17.5v. intv cc can also be connected to a power supply whose voltage is higher than 7.5v, and lower than v in , provided that supply does not exceed 17.5v. shdn/uvlo (pin 9): shutdown and undervoltage detect pin. an accurate 1.22v (nominal) falling threshold with externally programmable hysteresis detects when power is okay to enable switching. rising hysteresis is generated by the external resistor divider and an accurate internal 2a pull-down current. an undervoltage condition resets sort-start. tie to 0.4v, or less, to disable the device and reduce v in quiescent current below 1a. v in (pin 10): input supply pin. must be locally bypassed with a 0.22f, or larger, capacitor placed close to the pin. exposed pad (pin 11): ground. this pin also serves as the negative terminal of the current sense resistor. the exposed pad must be soldered directly to the local ground plane.
lt3757 8 3757fc b lock diagra m figure 1. lt3757 block diagram working as a sepic converter l1 r1 r3r4 m1 r2 l2 fbx 1.22v 2.5v d1 c dc c in v out c out2 c out1 c vcc intv cc v in r sense v isense ? + + v in i s1 2a 10 8 7 1 9 shdn/uvlo internal regulator and uvlo tsd 165?c a10 q3 vc vc 17.5v 2.7v up 2.6v down a8 uvlo i s2 10a i s3 c c1 c c2 r c driver slope sense gnd gate 108mv sr1 + ? + ? current limit ramp generator 7.2v ldo ? + ? + ? r o s 2.5v g1 rt r t ss c ss sync 1.25v 1.25v fbx fbx 1.6v ?0.8v + ? + ? + ? 2 3 5 4 + ? + ? 6 11 ramp pwm comparator frequency foldback 100khz-1mhz oscillator freq foldback freq prog 3757 f01 ? + + q1 a1 a2 1.72v ?0.88v + ? + ? a11 a12 a3 a4 a5 a6 g2 g5 g6 a7 a9 q2 g4 g3
lt3757 9 3757fc a pplica t ions i n f or m a t ion main control loop the lt3757 uses a fixed frequency, current mode control scheme to provide excellent line and load regulation. op- eration can be best understood by referring to the block diagram in figure 1. the start of each oscillator cycle sets the sr latch (sr1) and turns on the external power mosfet switch m1 through driver g2. the switch current flows through the external current sensing resistor r sense and generates a voltage proportional to the switch current. this current sense voltage v isense (amplified by a5) is added to a stabilizing slope compensation ramp and the resulting sum (slope) is fed into the positive terminal of the pwm comparator a7. when slope exceeds the level at the negative input of a7 (vc pin), sr1 is reset, turning off the power switch. the level at the negative input of a7 is set by the error amplifier a1 (or a2) and is an amplified version of the difference between the feedback voltage (fbx pin) and the reference voltage (1.6v or C0.8v, depending on the configuration). in this manner, the error amplifier sets the correct peak switch current level to keep the output in regulation. the lt3757 has a switch current limit function. the current sense voltage is input to the current limit comparator a6. if the sense pin voltage is higher than the sense current limit threshold v sense(max) (110mv, typical), a6 will reset sr1 and turn off m1 immediately. the lt3757 is capable of generating either positive or negative output voltage with a single fbx pin. it can be configured as a boost, flyback or sepic converter to gener - ate positive output voltage, or as an inverting converter to generate negative output voltage. when configured as a sepic converter, as shown in figure 1, the fbx pin is pulled up to the internal bias voltage of 1.6v by a voltage divider (r1 and r2) connected from v out to gnd. comparator a2 becomes inactive and comparator a1 performs the invert - ing amplification from fbx to vc. when the lt3757 is in an inverting configuration, the fbx pin is pulled down to C0.8v by a voltage divider connected from v out to gnd. comparator a1 becomes inactive and comparator a2 performs the noninverting amplification from fbx to vc. the lt3757 has overvoltage protection functions to protect the converter from excessive output voltage overshoot during start-up or recovery from a short-circuit condition. an overvoltage comparator a11 (with 20mv hysteresis) senses when the fbx pin voltage exceeds the positive regulated voltage (1.6v) by 8% and provides a reset pulse. similarly, an overvoltage comparator a12 (with 10mv hysteresis) senses when the fbx pin voltage exceeds the negative regulated voltage (C0.8v) by 11% and provides a reset pulse. both reset pulses are sent to the main rs latch (sr1) through g6 and g5. the power mosfet switch m1 is actively held off for the duration of an output overvoltage condition. programming turn-on and turn-off thresholds with the shdn/uvlo pin the shdn /uvlo pin controls whether the lt3757 is enabled or is in shutdown state. a micropower 1.22v reference, a comparator a10 and a controllable current source i s1 allow the user to accurately program the sup- ply voltage at which the ic turns on and off. the falling value can be accurately set by the resistor dividers r3 and r4. when shdn /uvlo is above 0.7v, and below the 1.22v threshold, the small pull-down current source i s1 (typical 2a) is active. the purpose of this current is to allow the user to program the rising hysteresis. the block diagram of the comparator and the external resistors is shown in figure 1. the typical falling threshold voltage and rising threshold voltage can be calculated by the following equations: v vin,falling = 1.22 ? (r3 + r4) r4 v vin,rising = 2a ? r3 + v in,falling
lt3757 10 3757fc a pplica t ions i n f or m a t ion for applications where the shdn/uvlo pin is only used as a logic input, the shdn/uvlo pin can be connected directly to the input voltage v in for always-on operation. intv cc regulator bypassing and operation an internal, low dropout (ldo) voltage regulator produces the 7.2v intv cc supply which powers the gate driver, as shown in figure 1. if a low input voltage operation is ex- pected (e.g., supplying power from a lithium-ion battery or a 3.3v logic supply), low threshold mosfets should be used. the lt3757 contains an undervoltage lockout comparator a8 and an overvoltage lockout comparator a9 for the intv cc supply. the intv cc undervoltage (uv) threshold is 2.7v (typical), with 100mv hysteresis, to ensure that the mosfets have sufficient gate drive voltage before turning on. the logic circuitry within the lt3757 is also powered from the internal intv cc supply. the intv cc overvoltage (ov) threshold is set to be 17.5v (typical) to protect the gate of the power mosfet. when intv cc is below the uv threshold, or above the ov thresh- old, the gate pin will be forced to gnd and the soft-start operation will be triggered. the intv cc regulator must be bypassed to ground im- mediately adjacent to the ic pins with a minimum of 4.7f ceramic capacitor. good bypassing is necessary to supply the high transient currents required by the mosfet gate driver. in an actual application, most of the ic supply current is used to drive the gate capacitance of the power mosfet. the on-chip power dissipation can be a significant concern when a large power mosfet is being driven at a high fre- quency and the v in voltage is high. it is important to limit the power dissipation through selection of mosfet and/ or operating frequency so the lt3757 does not exceed its maximum junction temperature rating. the junction tem- perature t j can be estimated using the following equations: t j = t a + p ic ? ja t a = ambient temperature ja = junction-to-ambient thermal resistance p ic = ic power consumption = v in ? (i q + i drive ) i q = v in operation i q = 1.6ma i drive = average gate drive current = f ? q g f = switching frequency q g = power mosfet total gate charge the lt3757 uses packages with an exposed pad for en - hanced thermal conduction. with proper soldering to the exposed pad on the underside of the package and a full copper plane underneath the device, thermal resistance ( ja ) will be about 43c/w for the dd package and 40c/w for the mse package. for an ambient board temperature of t a = 70c and maximum junction temperature of 125c, the maximum i drive (i drive(max) ) of the dd package can be calculated as: i drive(max) = (t j ? t a ) ( ja s v in ) ? i q = 1.28w v in ? 1.6ma the lt3757 has an internal intv cc i drive current limit function to protect the ic from excessive on-chip power dissipation. the i drive current limit decreases as the v in increases (see the intv cc minimum output current vs v in graph in the typical performance characteristics section). if i drive reaches the current limit, intv cc voltage will fall and may trigger the soft-start. based on the preceding equation and the intv cc minimum output current vs v in graph, the user can calculate the maximum mosfet gate charge the lt3757 can drive at a given v in and switch frequency. a plot of the maximum q g vs v in at different frequencies to guarantee a minimum 4.5v intv cc is shown in figure 2. as illustrated in figure 2, a trade-off between the operating frequency and the size of the power mosfet may be needed in order to maintain a reliable ic junction temperature. prior to lowering the operating frequency, however, be sure to check with power mosfet manufacturers for their most recent low q g , low r ds(on) devices. power mosfet manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly.
lt3757 11 3757fc a pplica t ions i n f or m a t ion figure 2. recommended maximum q g vs v in at different frequencies to ensure intv cc higher than 4.5v an effective approach to reduce the power consumption of the internal ldo for gate drive is to tie the intv cc pin to an external voltage source high enough to turn off the internal ldo regulator. if the input voltage v in does not exceed the absolute maximum rating of both the power mosfet gate-source voltage (v gs ) and the intv cc overvoltage lockout threshold voltage (17.5v), the intv cc pin can be shorted directly to the v in pin. in this condition, the internal ldo will be turned off and the gate driver will be powered directly from the input voltage, v in . with the intv cc pin shorted to v in , however, a small current (around 16a) will load the intv cc in shutdown mode. for applications that require the lowest shutdown mode input supply current, do not connect the intv cc pin to v in . in sepic or flyback applications, the intv cc pin can be connected to the output voltage v out through a blocking diode, as shown in figure 3, if v out meets the following conditions: 1. v out < v in (pin voltage) 2. 7.2 < v out < 17.5v 3. v out < maximum v gs rating of power mosfet a resistor r vcc can be connected, as shown in figure 3, to limit the inrush current from v out . regardless of whether figure 3. connecting intv cc to v out c vcc 4.7f v out 3757 f03 intv cc gnd lt3757 r vcc d vcc v in (v) 0 q g (nc) 200 250 150 100 10 20 5 15 30 40 25 35 50 0 300 3757 f02 300khz 1mhz or not the intv cc pin is connected to an external voltage source, it is always necessary to have the driver circuitry bypassed with a 4.7f low esr ceramic capacitor to ground immediately adjacent to the intv cc and gnd pins. operating frequency and synchronization the choice of operating frequency may be determined by on-chip power dissipation, otherwise it is a trade-off between efficiency and component size. low frequency operation improves efficiency by reducing gate drive cur - rent and mosfet and diode switching losses. however, lower frequency operation requires a physically larger inductor. switching frequency also has implications for loop compensation. the lt3757 uses a constant-frequency architecture that can be programmed over a 100khz to 1000khz range with a single external resistor from the rt pin to ground, as shown in figure 1. the rt pin must have an external resistor to gnd for proper operation of the lt3757. a table for selecting the value of r t for a given operating frequency is shown in table 1. table 1. timing resistor (r t ) value oscillator frequency (khz) r t (k) 100 140 200 63.4 300 41.2 400 30.9 500 24.3 600 19.6 700 16.5 800 14 900 12.1 1000 10.5
lt3757 12 3757fc a pplica t ions i n f or m a t ion the operating frequency of the lt3757 can be synchronized to an external clock source. by providing a digital clock signal into the sync pin, the lt3757 will operate at the sync clock frequency. if this feature is used, an r t resistor should be chosen to program a switching frequency 20% slower than sync pulse frequency. the sync pulse should have a minimum pulse width of 200ns. tie the sync pin to gnd if this feature is not used. duty cycle consideration switching duty cycle is a key variable defining converter operation. as such, its limits must be considered. minimum on-time is the smallest time duration that the lt3757 is capable of turning on the power mosfet. this time is generally about 220ns (typical) (see minimum on-time in the electrical characteristics table). in each switching cycle, the lt3757 keeps the power switch off for at least 220ns (typical) (see minimum off-time in the electrical characteristics table). the minimum on-time and minimum off-time and the switching frequency define the minimum and maximum switching duty cycles a converter is able to generate: minimum duty cycle = minimum on-time ? frequency maximum duty cycle = 1 C (minimum off-time ? frequency) programming the output voltage the output voltage (v out ) is set by a resistor divider, as shown in figure 1. the positive and negative v out are set by the following equations: v out,positive = 1.6v s 1+ r2 r1 ? ? ? ? ? ? v out,negative = ?0.8v s 1+ r2 r1 ? ? ? ? ? ? the resistors r1 and r2 are typically chosen so that the error caused by the current flowing into the fbx pin during normal operation is less than 1% (this translates to a maximum value of r1 at about 158k). soft-start the lt3757 contains several features to limit peak switch currents and output voltage (v out ) overshoot during start-up or recovery from a fault condition. the primary purpose of these features is to prevent damage to external components or the load. high peak switch currents during start-up may occur in switching regulators. since v out is far from its final value, the feedback loop is saturated and the regulator tries to charge the output capacitor as quickly as possible, resulting in large peak currents. a large surge current may cause inductor saturation or power switch failure. the lt3757 addresses this mechanism with the ss pin. as shown in figure 1, the ss pin reduces the power mosfet current by pulling down the vc pin through q2. in this way the ss allows the output capacitor to charge gradu- ally toward its final value while limiting the start-up peak currents. the typical start-up waveforms are shown in the typical performance characteristics section. the inductor current i l slewing rate is limited by the soft-start function. besides start-up, soft-start can also be triggered by the following faults: 1. intv cc > 17.5v 2. intv cc < 2.6v 3. thermal lockout any of these three faults will cause the lt3757 to stop switching immediately. the ss pin will be discharged by q3. when all faults are cleared and the ss pin has been discharged below 0.2v, a 10a current source i s2 starts charging the ss pin, initiating a soft-start operation. the soft-start interval is set by the soft-start capacitor selection according to the equation: t ss = c ss s 1.25v 10a
lt3757 13 3757fc a pplica t ions i n f or m a t ion fbx frequency foldback when v out is very low during start-up or a short-circuit fault on the output, the switching regulator must operate at low duty cycles to maintain the power switch current within the current limit range, since the inductor current decay rate is very low during switch off time. the minimum on-time limitation may prevent the switcher from attaining a sufficiently low duty cycle at the programmed switch- ing frequency. so, the switch current will keep increasing through each switch cycle, exceeding the programmed current limit. to prevent the switch peak currents from exceeding the programmed value, the lt3757 contains a frequency foldback function to reduce the switching frequency when the fbx voltage is low (see the normal- ized switching frequency vs fbx graph in the typical performance characteristics section). the typical frequency foldback waveforms are shown in the typical performance characteristics section. the frequency foldback function prevents i l from exceeding the programmed limits because of the minimum on-time. during frequency foldback, external clock synchroniza- tion is disabled to prevent interference with frequency reducing operation. thermal lockout i f lt3757 die temperature reaches 165c (typical), the part will go into thermal lockout. the power switch will be turned off. a soft-start operation will be triggered. the part will be enabled again when the die temperature has dropped by 5c (nominal). loop compensation loop compensation determines the stability and transient performance. the lt3757 uses current mode control to regulate the output which simplifies loop compensation. the optimum values depend on the converter topology, the component values and the operating conditions (including the input voltage, load current, etc.). to compensate the feedback loop of the lt3757, a series resistor-capacitor network is usually connected from the vc pin to gnd. figure 1 shows the typical vc compensation network. for most applications, the capacitor should be in the range of 470pf to 22nf, and the resistor should be in the range of 5k to 50k. a small capacitor is often connected in paral- lel with the rc compensation network to attenuate the v c voltage ripple induced from the output voltage ripple through the internal error amplifier. the parallel capacitor usually ranges in value from 10pf to 100pf. a practical approach to design the compensation network is to start with one of the circuits in this data sheet that is similar to your application, and tune the compensation network to optimize the performance. stability should then be checked across all operating conditions, including load current, input voltage and temperature. sense pin programming for control and protection, the lt3757 measures the power mosfet current by using a sense resistor (r sense ) between gnd and the mosfet source. figure 4 shows a typical waveform of the sense voltage (v sense ) across the sense resistor. it is important to use kelvin traces between the sense pin and r sense , and to place the ic gnd as close as possible to the gnd terminal of the r sense for proper operation. figure 4. the sense voltage during a switching cycle 3757 f04 v sense(peak) ?v sense = ? v sense(max) v sense t dt s v sense(max) t s
lt3757 14 3757fc a pplica t ions i n f or m a t ion due to the current limit function of the sense pin, r sense should be selected to guarantee that the peak current sense voltage v sense(peak) during steady state normal operation is lower than the sense current limit threshold (see the electrical characteristics table). given a 20% margin, v sense(peak) is set to be 80mv. then, the maximum switch ripple current percentage can be calculated using the following equation: = ? v sense 80mv ? 0.5 ? ? v sense c is used in subsequent design examples to calculate in- ductor value. ?v sense is the ripple voltage across r sense . the lt3757 switching controller incorporates 100ns timing interval to blank the ringing on the current sense signal immediately after m1 is turned on. this ringing is caused by the parasitic inductance and capacitance of the pcb trace, the sense resistor, the diode, and the mosfet. the 100ns timing interval is adequate for most of the lt3757 applications. in the applications that have very large and long ringing on the current sense signal, a small rc filter can be added to filter out the excess ringing. figure 5 shows the rc filter on sense pin. it is usually sufficient to choose 22 for r f lt and 2.2nf to 10nf for c flt . keep r f lt s resistance low. remember that there is 65a (typical) flowing out of the sense pin. adding r f lt will affect the sense current limit threshold: v sense_ilim n7ot3 f lt a pplication c ircuits the l t3757 can be configured as different topologies. the first topology to be analyzed will be the boost converter, followed by the flyback, sepic and inverting converters. boost converter: switch duty cycle and frequency the lt3757 can be configured as a boost converter for the applications where the converter output voltage is higher than the input voltage. remember that boost con- verters are not short-circuit protected. under a shorted output condition, the inductor current is limited only by the input supply capability. for applications requiring a step-up converter that is short-circuit protected, please refer to the applications information section covering sepic converters. the conversion ratio as a function of duty cycle is v out v in = 1 1? d in continuous conduction mode (ccm). for a boost converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v in(min) v out discontinuous conduction mode (dcm) provides higher conversion ratios at a given frequency at the cost of reduced efficiencies and higher switching currents. figure 5. the rc filter on sense pin c flt 3757 f05 lt3757 r flt r sense m1 sense gate gnd
lt3757 15 3757fc a pplica t ions i n f or m a t ion boost converter: inductor and sense resistor selection for the boost topology, the maximum average inductor current is: i l(max) = i o(max) ? 1 1? d max then, the ripple current can be calculated by: ? i l = ? i l(max) = ? i o(max) ? 1 1? d max the constant c in the preceding equation represents the percentage peak-to-peak ripple current in the inductor, relative to i l(max) . the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of ?i l requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of ?i l provides fast transient response and allows the use of low inductances, but results in higher input current ripple and greater core losses. it is recommended that c fall within the range of 0.2 to 0.6. given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value of the boost converter can be determined using the following equation: l = v in(min) ? i l ? f ? d max the peak and rms inductor current are: i l(peak) = i l(max) ? 1+ 2 ? ? ? ? ? ? i l(rms) = i l(max) ? 1+ 2 12 based on these equations, the user should choose the inductors having sufficient saturation and rms current ratings. set the sense voltage at i l(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 80mv i l(peak) boost converter: power mosfet selection important parameters for the power mosfet include the drain-source voltage rating (v ds ), the threshold voltage (v gs(th) ), the on-resistance (r ds(on) ), the gate to source and gate to drain charges (q gs and q gd ), the maximum drain current (i d(max) ) and the mosfets thermal resistances (r jc and r ja ). the power mosfet will see full output voltage, plus a diode forward voltage, and any additional ringing across its drain-to-source during its off-time. it is recommended to choose a mosfet whose b vdss is higher than v out by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the mosfet in a boost converter is: p fet = i 2 l(max) t 3 ds(on) t % max t 7 2 out t * l(max) t rss tg the first term in the preceding equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. for maximum efficiency, r ds(on) and c rss should be minimized. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet t ja = t a + p fet t jc + ca )
lt3757 16 3757fc a pplica t ions i n f or m a t ion figure 6. the output ripple waveform of a boost converter v out (ac) t on ?v esr ringing due to total inductance (board + cap) ?v cout 3757 f05 t off t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded. boost converter: output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desirable. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage plus any additional ringing across its anode-to-cathode during the on-time. the average forward current in normal operation is equal to the output current, and the peak current is equal to: i d(peak) = i l(peak) = 1+ 2 ? ? ? ? ? ? s i l(max) it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max) t7 d and the diode junction temperature is: t j = t a + p d t3 ja the r ja to be used in this equation normally includes the r jc for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step ?v esr and the charging/discharg- ing ?v cout . for the purpose of simplicity, we will choose 2% for the maximum output ripple, to be divided equally between ?v esr and ?v cout . this percentage ripple will change, depending on the requirements of the applica - tion, and the following equations can easily be modified. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the fol- lowing equation: esr cout 0.01 s v out i d(peak) boost converter: output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct output capacitors for a given output ripple voltage. the effect of these three parameters (esr, esl and bulk c) on the output voltage ripple waveform for a typical boost converter is illustrated in figure 6.
lt3757 17 3757fc a pplica t ions i n f or m a t ion for the bulk c component, which also contributes 1% to the total ripple: c out i o(max) 0.01 ? v out ? f the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 6. the rms ripple current rating of the output capacitor can be determined using the following equation: i rms(cout) i o(max) ? d max 1? d max multiple capacitors are often paralleled to meet esr requirements. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the required rms current rating. additional ceramic capaci- tors in parallel are commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. boost converter: input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input, and the input current wave- form is continuous. the input voltage source impedance determines the size of the input capacitor, which is typi - cally in the range of 10f to 100f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con- verter is: i rms(cin) t* l f lyback c onverter a pplications the lt3757 can be configured as a flyback converter for the applications where the converters have multiple outputs, high output voltages or isolated outputs. figure 7 shows a simplified flyback converter. the flyback converter has a very low parts count for mul - tiple outputs, and with prudent selection of turns ratio, can have high output/input voltage conversion ratios with a desirable duty cycle. however, it has low efficiency due to the high peak currents, high peak voltages and consequent power loss. the flyback converter is commonly used for an output power of less than 50w. the flyback converter can be designed to operate either in continuous or discontinuous mode. compared to con- tinuous mode, discontinuous mode has the advantage of smaller transformer inductances and easy loop compen- sation, and the disadvantage of higher peak-to-average current and lower efficiency. in the high output voltage applications, the flyback converters can be designed to operate in discontinuous mode to avoid using large transformers. figure 7. a simplified flyback converter r sense n p :n s v in c in c sn v sn l p d suggested rcd snubber i d i sw v ds 3757 f06 gate gnd lt3757 sense l s m + ? + ? r sn d sn ? + + c out +
lt3757 18 3757fc a pplica t ions i n f or m a t ion flyback converter: switch duty cycle and turns ratio the flyback converter conversion ratio in the continuous mode operation is: v out v in = n s n p ? d 1? d where n s /n p is the second to primary turns ratio. figure 8 shows the waveforms of the flyback converter in discontinuous mode operation. during each switching period t s , three subintervals occur: dt s , d2t s , d3t s . during dt s , m is on, and d is reverse-biased. during d2t s , m is off, and l s is conducting current. both l p and l s currents are zero during d3t s . the flyback converter conversion ratio in the discontinu- ous mode operation is: v out v in = n s n p ? d d2 according to the preceding equations, the user has relative freedom in selecting the switch duty cycle or turns ratio to suit a given application. the selections of the duty cycle and the turns ratio are somewhat iterative processes, due to the number of variables involved. the user can choose either a duty cycle or a turns ratio as the start point. the following trade-offs should be considered when select- ing the switch duty cycle or turns ratio, to optimize the converter performance. a higher duty cycle affects the flyback converter in the following aspects: t -pxfs .045 3.4 dvssfou * sw(rms) , but higher mosfet v ds peak voltage t -pxfs ejpef qfbl sfwfstf wpmubhf cvu ijhifs ejpef rms current i d(rms) t )jhifsusbotgpsnfsuvsotsbujp/ p /n s ) the choice, d d + d2 = 1 3 (for discontinuous mode operation with a given d3) gives the power mosfet the lowest power stress (the product of rms current and peak voltage). however, in the high output voltage applications, a higher duty cycle may be adopted to limit the large peak reverse voltage of the diode. the choice, d d + d2 = 2 3 (for discontinuous mode operation with a given d3) gives the diode the lowest power stress (the product of rms current and peak voltage). an extreme high or low duty cycle results in high power stress on the mosfet or diode, and reduces efficiency. it is recommended to choose a duty cycle, d, between 20% and 80%. figure 8. waveforms of the flyback converter in discontinuous mode operation 3757 f07 i sw v ds i d t dt s d2t s d3t s i sw(max) i d(max) t s
lt3757 19 3757fc a pplica t ions i n f or m a t ion flyback converter: transformer design for discontinuous mode operation the transformer design for discontinuous mode of opera- tion is chosen as presented here. according to figure 8, the minimum d3 (d3 min ) occurs when the converter has the minimum v in and the maximum output power (p out ). choose d3 min to be equal to or higher than 10% to guarantee the converter is always in discontinuous mode operation (choosing higher d3 allows the use of low inductances, but results in a higher switch peak current). the user can choose a d max as the start point. then, the maximum average primary currents can be calculated by the following equation: i lp(max) = i sw(max) = p out(max) d max ? v in(min) ? where h is the converter efficiency. if the flyback converter has multiple outputs, p out(max) is the sum of all the output power. the maximum average secondary current is: i ls(max) = i d(max) = i out(max) d2 where: d2 = 1 C d max C d3 the primary and secondary rms currents are: i lp(rms) = 2 ? i lp(max) ? d max 3 i ls(rms) = 2 ? i ls(max) ? d2 3 according to figure 8, the primary and secondary peak currents are: i lp(peak) = i sw(peak) t* lp(max) i ls(peak) = i d(peak) t* ls(max) the primary and second inductor values of the flyback converter transformer can be determined using the fol- lowing equations: l p = d 2 max ? v 2 in(min) ? 2 ? p out(max) ? f l s = d2 2 ? (v out + v d ) 2 ? i out(max) ? f the primary to second turns ratio is: n p n s = l p l s flyback converter: snubber design transformer leakage inductance (on either the primary or secondary) causes a voltage spike to occur after the mosfet turn-off. this is increasingly prominent at higher load currents, where more stored energy must be dis- sipated. in some cases a snubber circuit will be required to avoid overvoltage breakdown at the mosfets drain node. there are different snubber circuits, and application note 19 is a good reference on snubber design. an rcd snubber is shown in figure 7. the snubber resistor value (r sn ) can be calculated by the following equation: r sn = 2 ? v 2 sn ? v sn ? v out ? n p n s i 2 sw(peak) ? l lk ? f
lt3757 20 3757fc a pplica t ions i n f or m a t ion where v sn is the snubber capacitor voltage. a smaller v sn results in a larger snubber loss. a reasonable v sn is 2 to 2.5 times of: v out ? n p n s l lk is the leakage inductance of the primary winding, which is usually specified in the transformer characteristics. l lk can be obtained by measuring the primary inductance with the secondary windings shorted. the snubber capacitor value (c cn ) can be determined using the following equation: c cn = v sn ? v sn ? r cn ? f where ?v sn is the voltage ripple across c cn . a reasonable ?v sn is 5% to 10% of v sn . the reverse voltage rating of d sn should be higher than the sum of v sn and v in(max) . flyback converter: sense resistor selection in a flyback converter, when the power switch is turned on, the current flowing through the sense resistor (i sense ) is: i sense = i lp set the sense voltage at i lp(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 80mv i lp(peak) flyback converter: power mosfet selection for the flyback configuration, the mosfet is selected with a v dc rating high enough to handle the maximum v in , the reflected secondary voltage and the voltage spike due to the leakage inductance. approximate the required mosfet v dc rating using: bv dss > v ds(peak) where: v ds(peak) = v in(max) + v sn the power dissipated by the mosfet in a flyback con- verter is: p fet = i 2 m(rms) t3 ds(on) t7 2 ds(peak) t* l(max) t c rss tg the first term in this equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet t ja = t a + p fet t jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded.
lt3757 21 3757fc a pplica t ions i n f or m a t ion flyback converter: output diode selection the output diode in a flyback converter is subject to large rms current and peak reverse voltage stresses. a fast switching diode with a low forward drop and a low reverse leakage is desired. schottky diodes are recommended if the output voltage is below 100v. approximate the required peak repetitive reverse voltage rating v rrm using: v rrm > n s n p ? v in(max) + v out the power dissipated by the diode is: p d = i o(max) t7 d and the diode junction temperature is: t j = t a + p d t3 ja the r ja to be used in this equation normally includes the r jc for the device, plus the thermal resistance from the board to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. flyback converter: output capacitor selection the output capacitor of the flyback converter has a similar operation condition as that of the boost converter. refer to the boost converter: output capacitor selection section for the calculation of c out and esr cout . the rms ripple current rating of the output capacitors in discontinuous operation can be determined using the following equation: i rms(cout),discontinuous i o(max) ? 4 ? (3 ? d2) 3 ? d2 flyback converter: input capacitor selection the input capacitor in a flyback converter is subject to a large rms current due to the discontinuous primary current. to prevent large voltage transients, use a low esr input capacitor sized for the maximum rms current. the rms ripple current rating of the input capacitors in discontinuous operation can be determined using the following equation: i rms(cin),discontinuous p out(max) v in(min) ? ? 4 ? (3 ? d max ) 3 ? d max sepic c onverter a pplications the lt3757 can be configured as a sepic (single-ended primar y inductance converter), as shown in figure 1. this topology allows for the input to be higher, equal, or lower than the desired output voltage. the conversion ratio as a function of duty cycle is: v out + v d v in = d 1? d in continuous conduction mode (ccm). in a sepic converter, no dc path exists between the input and output. this is an advantage over the boost converter for applications requiring the output to be disconnected from the input source when the circuit is in shutdown. compared to the flyback converter, the sepic converter has the advantage that both the power mosfet and the output diode voltages are clamped by the capacitors (c in , c dc and c out ), therefore, there is less voltage ringing across the power mosfet and the output diodes. the sepic converter requires much smaller input capacitors than those of the flyback converter. this is due to the fact
lt3757 22 3757fc a pplica t ions i n f or m a t ion figure 9. the switch current waveform of the sepic converter 3757 f08 ?i sw = ? i sw(max) i sw t dt s i sw(max) t s that, in the sepic converter, the inductor l1 is in series with the input, and the ripple current flowing through the input capacitor is continuous. sepic converter: switch duty cycle and frequency for a sepic converter operating in ccm, the duty cycle of the main switch can be calculated based on the output voltage (v out ), the input voltage (v in ) and the diode forward voltage (v d ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out + v d v in(min) + v out + v d sepic converter: inductor and sense resistor selection as shown in figure 1, the sepic converter contains two inductors: l1 and l2. l1 and l2 can be independent, but can also be wound on the same core, since identical voltages are applied to l1 and l2 throughout the switching cycle. for the sepic topology, the current through l1 is the converter input current. based on the fact that, ideally, the output power is equal to the input power, the maximum average inductor currents of l1 and l2 are: i l1(max) = i in(max) = i o(max) s d max 1 ? d max i l2(max) = i o(max) in a sepic converter, the switch current is equal to i l1 + i l2 when the power switch is on, therefore, the maximum average switch current is defined as: i sw(max) = i l1(max) + i l2(max) = i o(max) s 1 1? d max and the peak switch current is: i sw(peak) = 1+ 2 ? ? ? ? ? ? s i o(max) s 1 1? d max the constant c in the preceding equations represents the percentage peak-to-peak ripple current in the switch, rela - tive to i sw(max) , as shown in figure 9. then, the switch ripple current ?i sw can be calculated by: ?i sw = c sw(max) the inductor ripple currents ?i l1 and ?i l2 are identical: ?i l1 = ?i l2 t* sw the inductor ripple current has a direct effect on the choice of the inductor value. choosing smaller values of ?i l requires large inductances and reduces the current loop gain (the converter will approach voltage mode). accepting larger values of ?i l allows the use of low in- ductances, but results in higher input current ripple and greater core losses. it is recommended that c falls in the range of 0.2 to 0.4.
lt3757 23 3757fc given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value (l1 and l2 are independent) of the sepic converter can be determined using the following equation: l1 = l2 = v in(min) 0.5 ? ? i sw ? f ? d max for most sepic applications, the equal inductor values will fall in the range of 1h to 100h. by making l1 = l2, and winding them on the same core, the value of inductance in the preceding equation is replaced by 2l, due to mutual inductance: l = v in(min) ? i sw ? f ? d max this maintains the same ripple current and energy storage in the inductors. the peak inductor currents are: i l1(peak) = i l1(max) t* l1 i l2(peak) = i l2(max) t* l2 the rms inductor currents are: i l1(rms) = i l1(max) ? 1+ 2 l1 12 where: l1 = ? i l1 i l1(max) i l2(rms) = i l2(max) ? 1+ 2 l2 12 where: l2 = ? i l2 i l2 (max) based on the preceding equations, the user should choose the inductors having sufficient saturation and rms cur - rent ratings. in a sepic converter, when the power switch is turned on, the current flowing through the sense resistor (i sense ) is the switch current. set the sense voltage at i sense(peak) to be the minimum of the sense current limit threshold with a 20% margin. the sense resistor value can then be calculated to be: r sense = 80 mv i sw(peak) sepic converter: power mosfet selection for the sepic configuration, choose a mosfet with a v dc rating higher than the sum of the output voltage and input voltage by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the mosfet in a sepic con- verter is: p fet = i 2 sw(max) t3 ds(on) t% max t7 in(min) + v out ) 2 t* l(max) t rss tg the first term in this equation represents the conduction losses in the device, and the second term, the switching loss. c rss is the reverse transfer capacitance, which is usually specified in the mosfet characteristics. for maximum efficiency, r ds(on) and c rss should be minimized. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following equation: t j = t a + p fet t ja = t a + p fet t jc + ca ) t j must not exceed the mosfet maximum junction temperature rating. it is recommended to measure the mosfet temperature in steady state to ensure that absolute maximum ratings are not exceeded. a pplica t ions i n f or m a t ion
lt3757 24 3757fc a pplica t ions i n f or m a t ion figure 10. a simplified inverting converter r sense c dc v in c in l1 d1 c out v out 3757 f09 + gate gnd lt3757 sense l2 m1 + ? + ? + sepic converter: output diode selection to maximize efficiency, a fast switching diode with a low forward drop and low reverse leakage is desirable. the average forward current in normal operation is equal to the output current, and the peak current is equal to: i d(peak) = 1+ 2 ? ? ? ? ? ? ? i o(max) ? 1 1? d max it is recommended that the peak repetitive reverse voltage rating v rrm is higher than v out + v in(max) by a safety margin (a 10v safety margin is usually sufficient). the power dissipated by the diode is: p d = i o(max) t7 d and the diode junction temperature is: t j = t a + p d t3 ja the r ja used in this equation normally includes the r jc for the device, plus the thermal resistance from the board, to the ambient temperature in the enclosure. t j must not exceed the diode maximum junction temperature rating. sepic converter: output and input capacitor selection the selections of the output and input capacitors of the sepic converter are similar to those of the boost converter. please refer to the boost converter, output capacitor selection and boost converter, input capacitor selection sections. sepic converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 1) should be larger than the maximum input voltage: v cdc > v in(max) c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? v out + v d v in(min) a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . i nver ting c onver ter a pplica tions the lt3757 can be configured as a dual-inductor inverting topology , as shown in figure 10. the v out to v in ratio is: v out ? v d v in = ? d 1? d in continuous conduction mode (ccm).
lt3757 25 3757fc inverting converter: switch duty cycle and frequency for an inverting converter operating in ccm, the duty cycle of the main switch can be calculated based on the negative output voltage (v out ) and the input voltage (v in ). the maximum duty cycle (d max ) occurs when the converter has the minimum input voltage: d max = v out ? v d v out ? v d ? v in(min) inverting converter: inductor, sense resistor, power mosfet, output diode and input capacitor selections the selections of the inductor, sense resistor, power mosfet, output diode and input capacitor of an inverting converter are similar to those of the sepic converter. please refer to the corresponding sepic converter sections. inverting converter: output capacitor selection the inverting converter requires much smaller output capacitors than those of the boost, flyback and sepic converters for similar output ripples. this is due to the fact that, in the inverting converter, the inductor l2 is in series with the output, and the ripple current flowing through the output capacitors are continuous. the output ripple voltage is produced by the ripple current of l2 flowing through the esr and bulk capacitance of the output capacitor: ? v out(p ? p) = ? i l2 ? esr cout + 1 8 ? f ? c out ? ? ? ? ? ? after specifying the maximum output ripple, the user can select the output capacitors according to the preceding equation. the esr can be minimized by using high quality x5r or x7r dielectric ceramic capacitors. in many applications, ceramic capacitors are sufficient to limit the output volt- age ripple. the rms ripple current rating of the output capacitor needs to be greater than: i rms(cout) ?t* l2 inverting converter: selecting the dc coupling capacitor the dc voltage rating of the dc coupling capacitor (c dc , as shown in figure 10) should be larger than the maximum input voltage minus the output voltage (negative voltage): v cdc > v in(max) C v out c dc has nearly a rectangular current waveform. during the switch off-time, the current through c dc is i in , while approximately Ci o flows during the on-time. the rms rating of the coupling capacitor is determined by the fol- lowing equation: i rms(cdc) > i o(max) ? d max 1? d max a low esr and esl, x5r or x7r ceramic capacitor works well for c dc . a pplica t ions i n f or m a t ion
lt3757 26 3757fc a pplica t ions i n f or m a t ion figure 11. 8v to 16v input, 24v/2a output boost converter suggested layout v in 3757 f10 v out l1 vias to ground plane d1 c out1 c out2 1 2 8 7 3 4 6 5 m1 c in r4 r c r1 r2 r ss r t r3 c vcc c c1 c c2 lt3757 1 2 3 4 5 9 10 6 7 8 r s board layout the high speed operation of the lt3757 demands careful attention to board layout and component placement. the exposed pad of the package is the only gnd terminal of the ic, and is important for thermal management of the ic. therefore, it is crucial to achieve a good electrical and thermal contact between the exposed pad and the ground plane of the board. for the lt3757 to deliver its full output power, it is imperative that a good thermal path be pro - vided to dissipate the heat generated within the package. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. to prevent radiation and high frequency resonance prob - lems, proper layout of the components connected to the ic is essential, especially the power paths with higher di/ dt. the following high di/dt loops of different topologies should be kept as tight as possible to reduce inductive ringing: ? in boost configuration, the high di/dt loop contains the output capacitor, the sensing resistor, the power mosfet and the schottky diode. ? in flyback configuration, the high di/dt primary loop contains the input capacitor, the primary winding, the power mosfet and the sensing resistor. the high di/ dt secondary loop contains the output capacitor, the secondary winding and the output diode. ? in sepic configuration, the high di/dt loop contains the power mosfet, sense resistor, output capacitor, schottky diode and the coupling capacitor. ? in inverting configuration, the high di/dt loop contains power mosfet, sense resistor, schottky diode and the coupling capacitor.
lt3757 27 3757fc table 2. recommended component manufacturers vendor components web address avx capacitors avx.com bh electronics inductors, transformers bhelectronics.com coilcraft inductors coilcraft.com cooper bussmann inductors bussmann.com diodes, inc diodes diodes.com fairchild mosfets fairchildsemi.com general semiconductor diodes generalsemiconductor.com international rectifier mosfets, diodes irf.com irc sense resistors irctt.com kemet capacitors kemet.com magnetics inc toroid cores mag-inc.com microsemi diodes microsemi.com murata-erie inductors, capacitors murata.co.jp nichicon capacitors nichicon.com on semiconductor diodes onsemi.com panasonic capacitors panasonic.com sanyo capacitors sanyo.co.jp sumida inductors sumida.com taiyo yuden capacitors t-yuden.com tdk capacitors, inductors component.tdk.com thermalloy heat sinks aavidthermalloy.com tokin capacitors nec-tokinamerica.com toko inductors tokoam.com united chemicon capacitors chemi-com.com vishay/dale resistors vishay.com vishay/siliconix mosfets vishay.com vishay/sprague capacitors vishay.com wrth electronik inductors we-online.com zetex small-signal discretes zetex.com a pplica t ions i n f or m a t ion check the stress on the power mosfet by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the pc board). beware of inductive ringing, which can exceed the maximum specified voltage rating of the mosfet. if this ringing cannot be avoided, and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche- rated power mosfet. the small-signal components should be placed away from high frequency switching nodes. for optimum load regula- tion and true remote sensing, the top of the output voltage sensing resistor divider should connect independently to the top of the output capacitor (kelvin connection), staying away from any high dv/dt traces. place the divider resis - tors near the lt3757 in order to keep the high impedance fbx node short. figure 11 shows the suggested layout of the 8v to 16v input, 24v/2a output boost converter. recommended component manufacturers some of the recommended component manufacturers are listed in table 2.
lt3757 28 3757fc typical a pplica t ions 3.3v input, 5v/10a output boost converter efficiency vs output current sense lt3757 v in v in 3.3v c in 22f 6.3v 2 v out 5v 10a 0.004 1w m1 41.2k 300khz gate fbx gnd intv cc shdn/uvlo sync rt ss vc 49.9k 34k 0.1f 6.8k 22nf 2.2nf 22 l1 0.5h d1 3757 ta02a 34k 1% 15.8k 1% c out1 150f 6.3v 4 c out2 22f 6.3v x5r 4 + c vcc 4.7f 10v x5r c in : taiyo yuden jmk325bj226mm c out1 : panasonic eefueoj151r c out2 : taiyo yuden jmk325bj226mm d1: mbrb2515l l1: vishay siliconix ihlp-5050fd-01 m1: vishay siliconix si4448dy output current (a) efficiency (%) 3757 ta02b 0.001 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10
lt3757 29 3757fc typical a pplica t ions 8v to 16v input, 24v/2a output boost converter efficiency vs output current load step response at v in = 12v sense lt3757 v in v in 8v to 16v c in 10f 25v x5r c vcc 4.7f 10v x5r v out 24v 2a r s 0.01 1w m1 r t 41.2k 300khz gate fbx gnd intv cc shdn/uvlo sync rt ss vc r3 200k r4 43.2k c ss 0.1f c c2 100pf r c 22k c c1 6.8nf l1 10h d1 3757 ta03a r2 226k 1% r1 16.2k 1% c out1 47f 35v 4 c out2 10f 25v x5r + c in , c out2 : murata grm31cr61e106ka12 c out1 : kemet t495x476k035as d1: on semi mbrs340t3g l1: vishay siliconix ihlp-5050fd-01 10h m1: vishay siliconix si4840bdp output current (a) 0.001 efficiency (%) 30 50 40 60 70 80 90 100 0.01 0.1 1 3757 ta03b 10 v in = 8v v in = 16v 500s/div v out 500mv/div (ac) 1.6a 0.4a i out 1a/div 3757 ta03c
lt3757 30 3757fc 2ms/div v out 100v/div 3757 ta04b 5s/div v out 5v/div (ac) v sw 20v/div 3757 ta04c typical a pplica t ions high voltage flyback power supply start-up waveforms switching waveforms sense lt3757 v in v sw v in 5v to 12v c in 47f 16v 4 intv cc c out 68nf 2 v out 350v 10ma 0.02 22 m1 140k 100khz gate fbx gnd shdn/uvlo danger! high voltage operation by high voltage trained personnel only sync rt ss vc ? ? 105k 46.4k 0.1f 220pf 100pf 6.8k 22nf t1 1:10 d1 c in : murata grm32er61c476k c out : tdk c3225x7r2j683k d1: vishay siliconix gsd2004s dual diode connected in series m1: vishay siliconix si7850dp t1: tdk dct15efd-u44s003 3757 ta04a 1m 1% 1m 1% 1.50m 1% 16.2k 1% 10nf c vcc 47f 25v x5r 22
lt3757 31 3757fc typical a pplica t ions 5.5v to 36v input, 12v/2a output sepic converter efficiency vs output current load step waveforms start-up waveforms frequency foldback waveforms when output short-circuits sense lt3757 v in v in 5.5v to 36v c in 4.7f 50v 2 c dc 4.7f 50v, x5r, 2 4.7f 10v x5r v out 12v 2a 0.008 1w m1 41.2k 300khz gate fbx gnd intv cc shdn/uvlo sync rt ss vc ? ? 105k 46.4k 0.1f 6.8nf 10k l1a l1b i l1b d1 c in , c dc : taiyo yuden umk316bj475kl c out1 : kemet t495x476k020as c out2 : taiyo yuden tmk432bj106mm d1: on semi mbrs360t3g l1a, l1b: coiltronics drq127-3r3 (*coupled inductors) m1: vishay siliconix si7460dp 3757 ta05a 105k 1% 15.8k 1% c out1 47f 20v 2 c out2 10f 25v x5r + v sw i l1a 500s/div v out 200mv/div (ac) 1.6a 0.4a i out 1a/div 3757 ta05c 2ms/div v out 5v/div i l1a + i l1b 5a/div 3757 ta05d v in = 12v 50s/div v out 10v/div v sw 20v/div i l1a + i l1b 5a/div 3757 ta05e v in = 12v output current (a) 0.001 20 efficiency (%) 30 40 50 60 70 80 90 100 0.01 0.1 1 3757 ta05b 10 v in = 16v v in = 8v
lt3757 32 3757fc typical a pplica t ions 5v to 12v input, 12v/0.4a output sepic converter nonisolated inverting slic supply sense lt3757 v in v in 5v to 12v c in1 1f 16v, x5r c in2 47f 16v c dc1 4.7f 16v, x5r c dc2 4.7f 16v x5r c out2 4.7f 16v, x5r 3 v out1 12v 0.4a v out2 ?12v 0.4a c out2 4.7f 16v, x5r 3 c vcc 4.7f 10v x5r 0.02 m1 30.9k 400khz d1, d2: mbrs140t3 t1: coiltronics vp1-0076 (*primary = 4 windings in parallel) m1: siliconix/vishay si4840bdy gate fbx gnd intv cc shdn/uvlo sync rt ss vc ? + 105k 46.4k 0.1f 100pf 22k 6.8nf t1 1,2,3,4 d1 gnd 1.05k 1% 158 1% d2 5 6 ? ? 3757 ta06 sense lt3757 v in v in 5v to 16v c in 22f 25v, x5r 2 c2 10f 50v x5r d1 dfls160 c vcc 4.7f 10v, x5r c3 22f 25v x5r c4 22f 25v x5r c out 3.3f 100v gnd c5 22f 25v x5r v out1 ?24v 200ma v out1 ?72v 200ma 0.012 0.5w m1 si7850dp 63.4k 200khz gate fbx gnd intv cc shdn/uvlo sync rt ss vc ? ? ? ? r2 105k r1 46.4k 0.1f 100pf 15.8k 464k 9.1k 10nf t1 1,2,3 4 d2 dfls160 5 d3 dfls160 6 vp5-0155 (primary = 3 windings in parallel) 3757 ta07
lt3757 33 3757fc p ackage descrip t ion 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer
lt3757 34 3757fc p ackage descrip t ion msop (mse) 0910 rev g 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ? 0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does not include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev g)
lt3757 35 3757fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 3/10 deleted bullet from features and last line of description updated entire page to add h-grade and military grade updated electrical characteristics notes and typical performance characteristics for h-grade and military grade revised ta04a and replaced ta04c in typical applications updated related parts 1 2 4 to 6 30 36 c 5/11 revised mp-grade temperature range in absolute maximum ratings and order information sections revised note 2 revised formula in applications information updated typical application drawing ta04a values revised typical application title ta06 2 4 19 30 32 (revision history begins at rev b)
lt3757 36 3757fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2008 lt 0511 rev c ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3758 boost, flyback, sepic and inverting controller 2.9v v in 100v, current mode control, 100khz to 1mhz programmable operation frequency, 3mm w 3mm 10-lead dfn and 10-lead msop-e packages lt3573 isolated flyback switching regulator with 60v integrated switch 3v v in 40v, no opto-isolator or third winding required, up to 7w, 16-lead msop-e package ltc1871/ltc1871 - 1/ l tc1871-7 boost, flyback and sepic controller, no r sense ?, low quiescent current adjustable switching frequency, 2.5v v in 36v, burst mode ? operation at light loads ltc3872 boost, flyback, sepic controller 2.75v v in 9.8v, 23-lead thinsot? and 2mm w 3mm 8-lead dfn packages lt3837 isolated no-opto synchronous flyback controller ideal for v in from 4.5v to 36v limited by external components, up to 60w, current mode control lt3825 isolated no-opto synchronous flyback controller v in 16v to 75v limited by external components, up to 60w, current mode control ltc3803/ltc3803 - 3/ l tc3803-5 200khz flyback dc/dc controller v in and v out limited only by external components, 6-lead thinsot package ltc3805/ltc3805-5 adjustable fixed 70khz to 700khz operating frequency flyback controller v in and v out limited only by external components, 3mm w 3mm 10-lead dfn, 10-lead msop-e packages high efficiency inverting power supply efficiency vs output current output current (a) 0.001 10 efficiency (%) 20 30 40 50 60 70 80 90 100 0.01 0.1 1 3757 ta08b 10 v in = 16v v in = 5v sense lt3757 v in v in 5v to 15v c in 47f 16v x5r c dc 47f 25v, x5r v out ?5v 3a to 5a 0.006 1w m1 si7848bdp 41.2k 300khz gate fbx gnd intv cc shdn/uvlo sync rt ss vc ? ? r2 105k r1 46.4k 0.1f 9.1k 10nf l1 l2 d1 mbrd835l l1, l2: coiltronics drq127-3r3 (*coupled inductors) 3757 ta08a 84.5k 16k c vcc 4.7f 10v x5r c out 100f 6.3v, x5r 2

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